Digital to pulse comparator apparatus



Aug. 16, 1966 G. G. STROHMEYER A DIGITAL T0 PULSE COMPARATOR APPARATUS Filed Sept. 16, 1963 4 Sheets-Sheet 1 REFERENCE PULSE OUTPUT IOI COMPARATOR BINARY COUNTER INVENTOR.

GARRY G. STROHMEYER A ORNEY Aug. 16, 1966 G. e. STROHMEYER DIGITAL TO PULSE COMPARATOR APPARATUS 4 Sheets-Sheet 5 Filed Sept.

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GARRY G. STROHMEYER NEY r' 3,267,429 Ice Patented August 16, 1966 3,267,429 DIGITAL T PULSE COMPARATOR APPARATUS Garry G. Strohmeyer, Hacienda Heights, Califi, assignor to Honeywell Inc., a corporation of Delaware Filed Sept. 16, 1963, Ser. No. 309,113 4 Claims. (Cl. 340-1462) binary counter which also provides a plurality of parallel binary digits output. The counter continuously counts from zero through its maximum desired count and then recycles. When the count in the binary counter coincides with the parallel binary digit word output of the memory circuit, the comparator circuit produces an output signal.

Each time the binary counter passes through a count of zero a reference output pulse is generated. One manner in which this reference pulse can be generated is by comparing the output of the binary counter with a fixed binary zero reference signal in a second comparator. In this manner when the binary counter passes through zero count the second comparator will produce the reference output pulse. If the output signal of the first comparator is compared with the reference output signal of the second comparator the time-value between the two pulses is proportional to the value of the binary number output of the memory circuit.

The binary counter generates a multiple-bit parallel output pattern ranging from binary xero through a maximum counter range. The maximum range of the counter is determined by the maximum expected binary output of the memory circuit. The binary counter stages are triggered simultaneously by an external clock signal so as to prevent any switching delay between the least and most significant binary stages. In the present invention such delays would result in. ambiguous output information.

The comparator portion of the invention must compare the plurality of outputs of the binary counter with the plurality of outputs from the memory and determine when these outputs are simultaneously coincident. The logical equation for the simultaneous coincidence of a plurality of inputs is:

If we let the letter B represent the output signal from the memory while the letter C represents the output signal from the binary counter, it can be seen that in order to determine the simultaneous coincidence of the two output signals it is necessary to have both the normal outputs and also the complementary outputs from both the memory circuit and from the binary counter. If we assume that the binary output of the memory and the binary output of the counter are each 12-bit numbers then we can see that it would require 48 inputs to the comparator circuit in order to determine the simultaneous coincidence of the two numbers.

However, if the logic of the comparator circuit is mechanized to satisfy the equation:

it may be seen that only the normal outputs from the memory circuit and the complementary outputs from the binary counter circuits are utilized. If we again assume that the binary numbers from both the memory and the counter are 12-bit numbers, then it can be seen that only a total of 24 inputs are required to the comparator circuit.

It is one object of this invention, therefore, to provide an improved digital to pulse converter circuit.

Another object of this invention is to .provide a digital to pulse converter wherein the time between two generated pulses is indicative of the value of a binary input.

A further object of this invention is to provide a digital to pulse converter which has a simplified logic mechanization.

These and other objects of my invention will become apparent to those skilled in the art upon consideration of the accompanying specification, claims, and drawings, of which:

FIGURE 1 is a block diagram representation of an embodiment of this invention;

FIGURES 2 and 3 are a schematic representation of a binary counter used in this invention; and

FIGURE 4 is a schematic representation of a compara tor circuit used in this invention.

STRUCTURE OF FIGURE 1 Referring to FIGURE 1 there is shown a memory unit 20 having a plurality of outputs 21-32 which are respectively connected to a plurality of inputs 33-44 of a comparator 45. Comparator 45 further has a plurality of inputs 46-57.

A binary counter 60 has an input 61 which is connected to the output of a source of clock pulses 62. Binary counter 60 further has a plurality of outputs 63-74 which are respectively connected to inputs 46-57 of comparator 45. Comparator 45 further has a signal pulse output line 75.

Outputs 63-74 of binary counter 60 are further connected to a plurality of inputs 76-87 of a comparator 88. Comparator 88 further has a plurality of inputs 89-100, which are connected to a fixed binary zero input number, and a reference pulse output line 101.

OPERATION OF FIGURE 1 Memory unit 20 represents any device capable of producing a parallel binary output representative of a given condition. For example,.assume that memory unit 20 produces a 12-bit parallel output representative of angular position. This binary output is represented by the digits B through B B being the lowest order bit and B being the highest order bit. If it is assumed that the binary output signal of memory unit 20 is representative of angular position in degrees and tenths of degrees then the binary number output of memory 20 will vary from 0000 0000 0000, representative of zero degrees angular position to binary 1110 00001111, representative of 359.9 degrees. This binary number is coupled to the inputs 33-44 of comparator circuit 45.

Clock pulse source 62 is connected to the input 61 of binary counter 60 and each clock pulse causes counter 60 to increment by one count. Since the maximum binary number from the output of memory 20 is equal to 3599 or binary 1110 0000 1111, it is necessary that the binary circuit 60 recycle after count 3599 It is evident that if the counter does not recycle after count 3599 the maximum count the counter would attain would be 4098, or binary 1111 1111 1111. The twelve flip-flops which comprise the binary counter are triggered simultaneously by the clock pulses from clock source 62. This prevents any switching delays between the least and most significant flip-flops.

The stages generating outputs 63-74 of binary counter 3 60 are connected to their respective flip-fiop stages of counter 60 so that the binary counter complement output appears on outputs 63-74. The binary counter output is represented by U through 6 The complementary outputs 6 through 6 of binary counter 60 are coupled to inputs 46-57 of comparator 45.

When each bit of the memory output is simultaneously coincident with each bit of the binary counter 60, the comparator Will produce an output pulse on the signal pulse output line 75.

The complementary output of binary counter is further connected through inputs 76-87 of comparator 88. Inputs 89-100 of comparator 88 are connected'to a fixed binary zero input. Therefore, when binary counter 60 registers a count of Zero, that is a binary number 0000 0000 0000, comparator 88 will produce an output pulse on the reference pulse output line 101. The time between the occurrence of the reference pulse on line 101 and the signal pulse on line is directly proportional to the magnitude of the binary number output from the memory unit 20.

STRUCTURE OF FIGURES 2 AND 3 FIGURES 2 and 3 show a schematic representation of the binary counter 60. Counter 60 comprises twelve flip-flops, flip-flops C through C being shown on FIG- URE 2 and flip-flops C through C being shown on FIGURE 3. The flip-flops used in counter 60 are clock triggered J-K type with inhibit type l-set and O-set inputs. A description of J-K type flip-flops can be found in Logic Design of Digital Computers, Montgomery Phister, John Wiley & Sons, 1958.

Referring to FIGURE 2 there is shown a C flip-flop having a clock input 110, a set 1 input 111, a set 0 input 112, a C output 113, and a 6 output 114. The C output 113 of flip-flop C is connected by means of a conductor 115 to an input 116 of a gate G to an input 120 of a gate G and to an input 23 of a gate G Gate G further has an input 117, gate G further has inputs 121 and 122, and gate 6;, further has inputs 124, 125 and 126. The O output 114 of flip-flop C is connected by means of a conductor 127 to a set 1 input 130 and a set 0 input 131 of flip-flop C Flip-flop C further has a clock input 129, a C output 132 and a 6 output 133. Output 132 of flip-flop C is connected by means of a conductor 134 to the input 117 of gate G to the input 125 of gate G and to the input 122 of gate G The output of gate G is connected through an inverter 135 to a set 1 input 136 and a set 0 input 137 of flip-flop C Flip-flop C further has a clock input 139, a C output 140 and a U output 141. Output 140 of flip-flop C is connected by means of a conductor 142 to the input 121 of gate G and to the input 124 of gate G The output of gate G is connected through an inverter amplifier 143 to a set 1 input 144 and a set 0 input 145 of flip-flop C Flip-flop 0.; further has a C output 146 and a U output 147 as well as a clock input 150. The output 146 of flip-flop C is connected to the input 126 of gate G The output of gate 6;, is connected through an inverting amplifier 151 and a conductor 152 to a set 0 input 153 of flip-flop C Flipfiop 0,; further has a set 1 input 154, a clock input 155, a C output 156, and a 6 output 157. The output of inverting amplifier 151 is further connected to an input of gate G The output of gate G is connected through an inverting amplifier 161 to a terminal 162. The output of inverting amplifier 161 is further connected by means of a conductor 163 to an input 165 of an AND gate G AND gate G further has an input 164 and an output connected through an inverting amplifier to input 154 of flip-flop C The output of inverting amplifier 161 is further connected by means of a conductor 166 to an input 167 of an AND gate G and by means of a conductor 172 to an input 173 of an AND gate G AND 4 a gate G further has an input and an input 171, while AND gate G further has an input 174.

The output of AND gate G is connected through an inverting amplifier 175 to a set 1 input 176 and a set 0 input 177 of flip-flop C Flip-flop C further has a clock input 180, a C output 181 and a 6 output 182. Output 156 of flip-flop C is connected to input 170 of AND' gateG and by means of a conductor 185 to the input 174 of AND gate G Output 156 of flip-flop C is further connected by means of a conductor 136 to an input of an AND gate G AND gate G further has an input'191 and an input 192. The output 181 of flip-flop C is connected by means of a conductor 193 to input 171 of AND gate G and by means of conductor 193 and a conductor 194 to the input 192 of AND gate G The output of AND gate G is connected through an inverting amplifier 196 to a set 1 input 197 and a set 0 input 198 of fiip-ilop C Flip-flop C further has a clock input 200, a C output 201 and a 6 output 202. Output 201 of flip-flop C is connected to input 191 of AND gate C The output of AND gate G is connected through an inverting amplifier 205 to an output terminal 206.

Output terminal 206 (see FIGURE 3) is connected to an input 207 of AND gate G The output of gate G is connected through an inverting amplifier 210 and a conductor 211 to an input 212 of an AND gate G through conductor 211 and a conductor 214 to an input 215 of an AND gate G through conductor 211 and a conductor 220 to an input 221 of an AND gate G AND gate G further has an input 213, AND gate G further has an input 216, and an input 217, AND gate G further has an input 222, and input 223, and an input 224.

The output of inverting amplifier 210 is further connected to an input 230 of an AND gate G AND gate G further has an input 231 and an input 232.

Terminal 162, which is connected to the output of inverting amplifier 161 of FIGURE 2, is connected by means of a conductor 233 to the input 213 of AND gate G The output of AND gate G is connected through an inverting amplifier 234 to a set 1 input 235 and a set 0 input 236 of flip-flop C Flip-flop C fur-ther has a clock input 237, a C output 240, and a U output 241.

Terminal 162 is further connected by means of a conductor 242 to the input 216 of AND gate G by means of conductor 242 and a conductor 243 to an input 244 of an AND gate G by means of conductor 242 and a conductor 250 to the input 231 of AND gate G and by means of conductors 242, 250, and 251 to the input 223 of AND gate G AND gate G further has inputs 245, 246 and 247.

Output 240 of flip-lop C is connected by means of a conduct-or 252 to the input 232 of AND gate G and by means of conductor 252 and conductor 253 to an input 254 of AND gate G AND gate G further has an input 255.

The output of AND gate G is connected through an inverting amplifier 256 to a set 1 input 260 and a set 0 input 261 of flip-flop C Flip-flop C further has a clock input 262, a C output 263 and a U out-put 264. The output 263 of flip-flop C is connected to the input 255 of AND gate G The output of AND gate G is connected through an inverting amplifier 266 to an input 267 of gate G The output of gate G is connected through an inverting amplifier 270 and a conductor 271 to the input 217 of AND gate G The output of inverting amplifier 270 is further connected by means of a conductor 272 to the input 222 of AND gate G The output of AND gate G is connected through an inverting amplifier 275 to a set 1 input 276 of flip-flop C Flip-flop C further has a set 0 input 277, a clock input 280, a C output 281, and a D output 282. Output 281 of flip-flop C is connected by means of a con- 5 ductor 283 to input 245 of AND gate G and to input 224 of AND gate G The output of AND gate G is connected through an inverting amplifier 284 to an input 285 of gate G to a set 1 input 286 of flip-flop C and to an input 294 of an AND gate G Flip-flop C further has a set input 287, a clock input 290, a C output 291, and a (i output 292, while AND gate G further has an input 295.

The output 291 of flip-flop C is connected by means of a conductor 296 to the input 247 of AND gate G and to an input 297 of an AND gate G AND gate G further has an input 298. The output of gate G is connected through inverting amplifier 300 to the input 298 of AND gate G .The output of AND gate G is connected through an inverting amplifier 301 to a set 1 input 302 of flip-flop C Flip-flop C further has a set 0 input 303, a clock input 304,-a C output 305, and a 6 output 306. Output 305 of flip-flop C is connected by meansof a conductor. 307 to the input 246 of AND gate G The output of AND gate G is connected to the input of an inverting amplifier 310. The output of inverting amplifier 310 is connected by means of a conductor 311 to the input 295 of AND gate G and to input 303 of flip-flop C12, and by means of conductor 311 and a conductor 312 to a terminal 31.3. Terminal 313 (see FIG- URE 2) is connected by means of a conductor to the input 164 of AND gate G The output of AND gate G is connected through an inverting amplifier 315 and a conductor 316 to an input 317 of gate G The output of gate G is connected through an inverting amplifier 320 to the set 0 input 277 of flip-flop C The output of inverting amplifier 315 is further connected by means of a conductor 321 to an input 322 of gate G The output of gate G isconnected through an inverting amplifier 323 to the set 0 input 287 of flip-flop C OPERATION OF FIGURES 2 AND 3 As mentioned previously, each time a count is registered in counter 60, each of the twelve flip-flops, C through C are triggered simultaneously by the clock signal Since eachof the flip-flops are triggered by the clock signal it is necessary to provide inhibit logic to the various set 1 and set 0 inputs of the flip-flops so that only the correct flip-flops change state. The counter circuit shown in FIGURES 2 and 3 is designed to provide a countfrom zero to 3599, or in binary notation from .0000 0000 0000 to 1110 0000 1111. It is necessary to recycle the counter 60 after the count reaches 1110 0000 1111 since in the illustrationassume the converter is converting from a binary representation of angular position to a pulse representative of angular position, the angular data being expressed in degrees and tenths of degrees. The logic output equations for each of the gates G through G are set forth below in Equations 3 through 23. In these equations the output is considered from the output of the gate and its associated inverting amplifier. For example, the output-of gate G would be from the output of inverting amplifier 135.

8' 9' 10+ 1 z 3' 4' 1u' 11' 12 2Q= 15= 1' 2' a' 4 5' s 7' a' Q' m 21= 20 11= 1 2' 3 4' s' s' 'i a' s io u As can be seen from FIGURES 2 and 3, the triggering of the various flip-flops of the counter is determined by the output of the selected gate circuits. For example, the output of gate circuit G determines the triggering of flip-flop C while the output of gate G determines the triggering of flip-flop C As can be seen from the drawings, flip-flops C C C C C C C and C have set 1 and set 0 inputs connected in common, while flip-flops C C C and C each have their set 1 and set 0 inputs connected to individual gates. For examples, the set 1 input of flip-flop C is connected to the output of gate G while the set 0 input of flip-flops C is connected to the output of gate G The logic equations for each of the flip-flops of counter 60 are set forth below, with the separate set 0 and set 1 equations of flip-flops C C C and C also being indicated.

Referring to FIGURE 4 the-re is shown a plurality of OR gates 340-351, each having first and second inputs and an output. One input from each of the OR gates 7 Each output of the OR gates 340-351 is connected to a separate input of an AND gate 355. The output of AND gate 355 is connected through an inverting amplifier 356 to an input of an OR gate 357.

A plurality of AND gates 360-371 each have a first and second input and an output. One input from each of the AND gates 360-371 is connected to a separate bit of the output number B through B from the output of memory 20 while the other input of each of the AND gates 360-371 is connected to a separate bit of the output number O through U from the output of binary counter 60. The outputs of AND gates 360-371 are each connected to separate inputs of OR gate 357. The output of OR gate 357 is connected through an inverting amplifier 372 and an amplifier 373 to the output signal terminal 75.

OPERATION OF FIGURE 4 As can be seen by referring to Equation 2, the equation for a comparator for comparing 12-bit binary input numbers is as follows:

gether in OR gates 340-351. For example, the output of OR gate 340 will be The output of OR gate 341 will be (42) B +U and the output of OR gate 351 will be 43 1Z+ 1Z The outputs from OR gates 340-351 are ANDed together in AND gate 355 and are inverted by inverter 356 so that the output of inverter 356 is Each corresponding bit of the binary number B through B from the output of memory 20 and the binary number U through 6 tonm the output of binary counter 60 and are ANDed together in AND circuits 360-371 so that the output of AND gate 360 is l' l The output of AND gate 361 is 2 2 The output of AND gate 362 is The output of AND gates 360-371 and the output from inverting amplifier 356 are ORd together in OR gate 357. The output of OR gate 357 is inverted in inverting amplifier 372 and is amplified in amplifier 373 and appears at output signal terminal 374. A pulse will appear at output terminal 75 when the binary number from the memory unit 20 and the binary number in the binary counter 60 are simultaneously coincident.

In order to generate the reference pulse output from the comparator 88 shown in FIGURE 1, a comparator which is structurally the same as that shown in FIGURE 4 could be used, the only difference being that instead of the binary number B through B being fed to the OR gate and AND gate input terminals the binary number would be fed to these terminals instead. In this manner when the binary counter 60 recycled through 0, comparator 88 would produce a reference pulse output at the output signal terminal.

It is to be understood that while I have shown a specific embodiment of my invention that this is for the purpose of illustration only and that my invention is to be limited solely by the scope of the appended claims.

I claim:

1. Digital comparing apparatus comprising:

a memory circuit having a binary number output B B B where the subscripts indicate the order of the binary number bit;

a binary counter having a complement output means for ORing like order bits of the memory circuit output and the counter circuit output to produce first signals B +T B -I-U B +U means for ANDing and inverting the first signals to produce a second signal F -C +F -C F -C means for ANDing like order bits of the memory circuit output and the counter circuit output to produce third signals B 6 3 -6 B -fi and means for ORing and inverting said second signal and said third signals to produce an output signal indicative of correspondence between the binary number output of said memory circuit and a count in said binary counter.

2. Digital comparing apparatus comprising:

a memory circuit having a parallel binary number outa binary counter having a plurality of stages equal to the number of bits in the parallel binary number output of said memory circuit, each of the counter stages providing a complement output;

a plurality of first OR gates having inputs and outputs;

means respectively connecting each bit of the binary number output of said memory circuit and the respective order complement bit output of said binary counter to the inputs of a separate one of said plurality of first OR gates;

a first AND gate having a plurality of inputs and an output;

means connecting the outputs of said plurality of first OR gates to the plurality of inputs of said first AND gate;

means connecting the output of said first AND gate to a first inverter;

a plurality of second AND gates having inputs and outputs;

means respectively connecting each bit of the binary number output of said memory circuit and the respective order complement bit output of said binary counter to the inputs of a separate of said plurality of second AND gates;

a second OR gate having a plurality of inputs and an output;

means connecting the outputs of said plurality of second AND gates and the output of said first inverter to the plurality of inputs of said second OR gate; and

means connecting the output of said second OR gates through an inverter to an output.

3. Digital comparing apparatus comprising:

a memory circuit having a binary number output B B B where the subscripts indicate the order of the binary number bit;

a binary counter having a complement output means connected to the complement output of said binary counter to produce a reference pulse each time the count in said counter is at a predetermined value;

means for ORing like order bits of the memory circuit output and the counter circuit output to produce first signals B +F B -l-U l B d-fi means for ANDing and inverting the first signals to produce a second signal F -C +F C T' -C means for ANDing like order bits of the memory circuit output and the counter circuit output to produce third signals B 6 B -fi B -U and means for ORing and inverting said second signal and said third signals to produce an output signal indicative of correspondence between the binary number output of said memory circuit and a count in said binary counter, the time between said reference pulse and said output signal being indicative of the value of the output binary number of said memory circuit.

4. Digital comparing apparatus comprising:

a memory circuit having a binary number output B B B where the subscripts indicate the order of the binary number bit;

a binary counter having a complement output first gating means for combining said binary number output from said memory circuit and said output from said counter to produce a first signal F1'C1+ B3'C2 F C and second gating means for combining said binary number output from said memory circuit and said output from said counter With said first signal to produce a second signal indicative of ANDed combinations of like ordered bits of the memory circuit output and the counter output being ORed with said first signal, said second signal being indicative of the equality of the memory circuit output and the counter output.

References Cited by the Examiner UNITED STATES PATENTS 6/1963 Wychorski et al. 340146.2 4/1964 Venn et al. 23592 MALCOLM A. MORRISON, Primary Examiner.

M. I. SPIVAK, Assistant Examiner. 

1. DIGITAL COMAPRING APPARATUS COMPRISING: A MEMORY CIRCUIT HAVING A BINARY NUMBER OUTPUT B1, B2 ... BN WHERE THE SUBSCRIPTS INDICATE THE ORDER OF THE BINARY NUMBER BIT; A BINARY COUNTER HAVING A COMPLEMENT OUTPUT C1, C2 ... CN; MEANS FOR OR''ING LIKE ORDER BITS OF THE MEMORY CIRCUIT OUTPUT AND THE COUNTER CIRCUIT OUPTUT TO PRODUCE FIRST SIGNALS B1+C1, B2+C2 ... BN+CN; MEANS FOR AND''ING AND INVERTING THE FIRST SIGNALS TO PRODUCE A SECOND SIGNAL B1.C1+B2.C2 ... BN.CN; MEANS FOR AND''ING LIKE ORDER BITS OF THE MEMORY CIRCUIT OUTPUT AND THE COUNTER OUTPUT TO PRODUCE THIRD SIGNALS B1.C1,B2.C2 ... BN.CN; AND 